<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>VHDL code on ENSEIRB-MATMECA</title><link>https://emmk-73cb1c.gitlab.io/fr/notes/vhdl/</link><description>Recent content in VHDL code on ENSEIRB-MATMECA</description><generator>Hugo -- gohugo.io</generator><language>fr</language><atom:link href="https://emmk-73cb1c.gitlab.io/fr/notes/vhdl/index.xml" rel="self" type="application/rss+xml"/><item><title>Syntaxe VHDL</title><link>https://emmk-73cb1c.gitlab.io/fr/notes/vhdl/syntax/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://emmk-73cb1c.gitlab.io/fr/notes/vhdl/syntax/</guid><description>&lt;div class="note-card ">
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&lt;h5 class="note-title">&lt;span>VHDL: Entity&lt;/span>&lt;/h5>
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&lt;div class="card-body">&lt;div class="highlight">&lt;pre tabindex="0" style="color:#f8f8f2;background-color:#272822;-moz-tab-size:4;-o-tab-size:4;tab-size:4;">&lt;code class="language-vhdl" data-lang="vhdl">&lt;span style="display:flex;">&lt;span>&lt;span style="color:#66d9ef">entity&lt;/span> &lt;span style="color:#a6e22e">my_entity&lt;/span> &lt;span style="color:#66d9ef">is&lt;/span>
&lt;/span>&lt;/span>&lt;span style="display:flex;">&lt;span> &lt;span style="color:#66d9ef">port&lt;/span>(
&lt;/span>&lt;/span>&lt;span style="display:flex;">&lt;span> i_in &lt;span style="color:#f92672">:&lt;/span> &lt;span style="color:#66d9ef">in&lt;/span> &lt;span style="color:#66d9ef">std_logic&lt;/span>;
&lt;/span>&lt;/span>&lt;span style="display:flex;">&lt;span> o_out &lt;span style="color:#f92672">:&lt;/span> &lt;span style="color:#66d9ef">out&lt;/span> &lt;span style="color:#66d9ef">std_logic&lt;/span>);
&lt;/span>&lt;/span>&lt;span style="display:flex;">&lt;span>&lt;span style="color:#66d9ef">end&lt;/span> &lt;span style="color:#a6e22e">my_entity&lt;/span>;
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&lt;h5 class="note-title">&lt;span>VHDL: Architecture&lt;/span>&lt;/h5>
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&lt;div class="card-body">&lt;div class="highlight">&lt;pre tabindex="0" style="color:#f8f8f2;background-color:#272822;-moz-tab-size:4;-o-tab-size:4;tab-size:4;">&lt;code class="language-vhdl" data-lang="vhdl">&lt;span style="display:flex;">&lt;span>&lt;span style="color:#66d9ef">architecture&lt;/span> &lt;span style="color:#a6e22e">my_arch&lt;/span> &lt;span style="color:#66d9ef">of&lt;/span> &lt;span style="color:#a6e22e">my_entity&lt;/span> &lt;span style="color:#66d9ef">is&lt;/span>
&lt;/span>&lt;/span>&lt;span style="display:flex;">&lt;span> &lt;span style="color:#66d9ef">begin&lt;/span>
&lt;/span>&lt;/span>&lt;span style="display:flex;">&lt;span>
&lt;/span>&lt;/span>&lt;span style="display:flex;">&lt;span>&lt;span style="color:#66d9ef">end&lt;/span> &lt;span style="color:#a6e22e">my_arch&lt;/span>;
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