VHDL: Entity
entity my_entity is
port(
i_in : in std_logic;
o_out : out std_logic);
end my_entity;
VHDL: Architecture
architecture my_arch of my_entity is
begin
end my_arch;
entity my_entity is
port(
i_in : in std_logic;
o_out : out std_logic);
end my_entity;
architecture my_arch of my_entity is
begin
end my_arch;